1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device which has a self-diagnosis function to determine for every chip whether or not the semiconductor integrated circuit device is good in performance.
2. Description of Related Art
In recent years, the high integration, high density and high performance of a semiconductor integrated circuit device proceed remarkably. For this reason, various problems occur in a manufacture process.
One of such problems is that the performance of the semiconductor integrated circuit device changes because of a distribution of characteristics of MOS transistors in the circuit device due to change of parameters in the manufacturing process. As a result, the performance of the circuit device becomes close to a performance limit, especially an operation speed limit of the circuit devices requested by customers. Therefore, there has increased the generation rate of the products which can operate but do not meet the required operation speed.
The performance distribution width of the circuit devices is possible to be reduced if manufacture standards in the wafer manufacturing process are made severe. In such a case, however, there is another problem in that it is difficult that all chips on the semiconductor wafer satisfy the manufacturing standards. For this reason, it is necessary to change the management in the manufacture of the semiconductor integrated circuit devices from the wafer-based management to the chip-based management. Thus, the need to determine whether the performance of every circuit device falls within the product standard has been increased.
A conventional semiconductor integrated circuit device having such a determining circuit is disclosed in Japanese Laid Open Patent Disclosure (JP-A-Showa 62-274635) as the first reference which corresponds to U.S. patent application Ser. No. 06/863,094 filed on May 14, 1986, now abandoned, or Japanese Laid Open Patent Disclosure (JP-A-Heisei 2-140947) as the second reference. The conventional semiconductor integrated circuit device of the second reference has a circuit structure shown in FIG. 1. Referring to FIG. 1, the conventional semiconductor integrated circuit device is composed of a transistor Tr10 as a test target which is connected between an external terminal O10 and a ground line, a transistor Tr12 which is connected between an external terminal O11 and the gate electrode of the transistor Tr10, and a transistor Tr11 which is connected between the gate electrode of the transistor Tr10 and the ground line. Either of the transistor Tr11 and the transistor Tr12 is turned on based on the state of a test signal TEST, i.e., whether the test signal TEST is "0" or "1".
In a case where the transistor Tr12 is turned on, a drain voltage and a gate voltage are supplied from the external terminals O10 and O11 to the drain and gate of the transistor Tr10, respectively. Thereby, the characteristic of the transistor Tr10 as the test target can be measured. On the other hand, in a case where the transistor Tr11 is turned on, the transistor Tr10 is turned off. In addition, an output buffer Buf10 and an output buffer Buf11 are activated. As a result, the output signals of these output buffers Buf10 and Buf11 are outputted to the external terminals O10 and O11, respectively.
There is the following problems in the conventional semiconductor integrated circuit device shown in FIG. 1. That is, the first problem is in that an additional external input terminal is required to externally input the test signal TEST to the conventional semiconductor integrated circuit device and to measure the transistor as the test target, as shown in FIG. 1. In the semiconductor integrated circuit device, the number of external terminals has increased more and more as the high integration and achievement of multi-functions. For this reason, it is necessary to avoid use of any external terminal even for measurement of a transistor characteristic.
Another problem of the conventional semiconductor integrated circuit device shown in FIG. 1 is in that special test facilities are required such as a digital signal source, an analog signal source and an analog tester to measure the characteristic of the transistor as the test target. Especially, in a case where an analog signal is inputted and measured, it is not easy to reduce noise generated from the test facilities in measurement. For this reason, there is caused a problem that the test facilities themselves must be made to have high precision, resulting in a high price of the test facilities. Also, as the high integration and achievement of multi-function of the semiconductor integrated circuit device, the test takes a long time. It derives increase in cost of the semiconductor integrated circuit device. Also, the measurement using the analog signal requires the long measurement time compared to the measurement using a digital signal. Therefore, the measurement using the analog signal should be avoided.
In order to solve the problems of the above semiconductor integrated circuit device, the inventor of the present invention proposed in Japanese Laid Open Patent Disclosure (JP-A-Heisei 7-94683: corresponding to Japanese Patent Application No. Heisei 5-239341) an improved semiconductor integrated circuit device whose circuit structure was shown in FIGS. 2 and 3. FIG. 2 is a block diagram illustrating the circuit structure of the proposed semiconductor integrated circuit device and FIG. 3 is a circuit diagram illustrating the circuit structure of a diagnostic circuit 20 in FIG. 2. The circuit structure is composed of means for self-diagnosing whether the performance of a semiconductor device falls within the manufacture standard for every chip, and means for determining whether or not the integrated circuit device is good, for every chip in accordance with a signal indicative of the diagnosis result.
Referring to FIG. 2, the conventional semiconductor integrated circuit device is composed of a signal processing circuit 10 and a diagnostic circuit 20. The signal processing circuit 10 is connected to an external input terminal 1 to which a predetermined logic input signal is inputted and an external output terminal 2 from which a logic signal obtained by processing the logic input signal is outputted. The diagnostic circuit 20 self-diagnoses whether each of transistors Q1, Q2, Q3 and Q4 of the signal processing circuit 10 is in a good performance state. The diagnostic circuit 20 is composed of a diagnostic transistor QDDT having the same size as at least one of the transistors Q1 to Q4 and a reference transistor QREF used as a reference in comparison of the performance. That the transistors have the same size means that the gate length and the gate width are the same at least between the transistors. Whether the characteristic of the transistor QDDT is good is diagnosed by comparing the drain current of the diagnostic transistor QDDT and the drain current of the reference transistor QREF.
Referring to FIG. 3, the diagnostic circuit 20 is composed of a comparing circuit to compare the characteristic of the reference transistor QREF and that of the diagnostic transistor QDDT which represents the transistors of the signal processing circuit 10. In a case where the characteristic of the diagnostic transistor QDDT is not in a range determined based on that of the reference transistor QREF, the diagnostic transistor QDDT is determined not to satisfy the manufacture standard. A signal is generated on an output terminal 5 in accordance with the determining result. The external output terminal 2 for the signal processing circuit 10 is set to either of the output enable state or the high impedance state based on this signal.
Referring to FIG. 3 again, in a usual comparing circuit, two transistors located on symmetric position are designed to have the same gate length and the same gate width. This is because the mutual conductances of these two transistors should be kept to be same, so that the symmetry of the circuit should be kept, even If the gate length and gate width of the transistor are changed from the design values in the manufacturing process. In FIG. 3, for example, the transistor Q6A and the transistor Q6B are designed to have the same size. Similarly, the transistors Q7A and Q7B, the transistors Q8A and Q8B, and the transistors QDDT and QREF are also designed to have the same sizes, respectively. In this circuit structure, signals are inputted to the input terminal 3A and 3B respectively and compared with each other. A logic signal of "1" or "0" is outputted to the external output terminal 5 (the output terminal of Inverter 6) in accordance with the comparing result.
The comparing circuit used for this conventional semiconductor integrated circuit device is designed to detect the difference in drain current between the two transistors QDDT and QREF, unlike a usual method of comparing the amplitudes of two input signals, to be mentioned later. Therefore, a common potential is given to two input terminals 3A and 3B. That is, the gate electrode of each of the transistors QDDT and QREF is connected to a higher potential power supply line 4. The drain current IREF of the reference transistor QREF is folded back by the first current mirror circuit which is composed of transistors Q6B and Q7B and is inputted to the input terminal (the drain of the transistor Q8B) of the second current mirror circuit which is composed of the transistors Q8A and Q8B. On the other hand, the drain current IDDT of the diagnostic transistor QDDT is folded back by the third current mirror circuit which is composed of the transistors Q6A and Q7A. The inverter 6' which is connected to the connection node between the output terminals (the drains of the transistors Q7A and Q8A) of the second and third current mirror circuits, logically inverts a voltage signal corresponding to the difference between the currents IDDT and IREF and outputs to the output terminal 5 as a binary logic signal through an inverter 6.
Note that two transistors QDDT and QREF are designed to have substantially the same mutual conductances, i.e., the same ratio (W/L) of the gate width (W) to the gate length (L). However, the absolute values of the gate width and gate length of the transistor QREF are much larger than those of the transistor QDDT. On the other hand, the gate width and gate length of the transistor QDDT are the same in size as those of either of the MOS transistors Q1, Q2, Q3 and Q4 which are used in the signal processing circuit 10. This is because the reference transistor QREF keeps a predetermined mutual conductance as a comparison reference without undergoing any influence even if the gate width and gate length of each of the transistors are changed from the design values due to deviations of parameters in the wafer manufacturing process, to be mentioned later.
The Japanese Laid Open Patent Disclosure (JP-A-Showa 61-46613) discloses a level detecting circuit in which a detection level does not change even if a threshold voltage of a MOS-FET changes, but a stabilized voltage and a signal voltage to be tested are supplie d to MOS transistors of a comparing circuit, respectively, unlike the second reference.
The operation of the conventional semiconductor integrated circuit device of the second reference shown In FIG. 2 will be described below, in conjunction with the method of diagnosing whether the transistor characteristic is good, taking as an example the case where the gate length of the transistor becomes shorter than the design value in the wafer manufacturing process so that the performance of the transistor is changed from the design performance values. FIG. 4 is a graph illustrating a relation of threshold voltage and the gate length of the MOS transistor. In FIG. 4, the gate length L1 is the design gate lengths of each of the MOS transistors in the signal processing circuit 10 and the diagnostic transistor QDDT in the diagnostic circuit 20 and it is, for example, 0.5 .mu.m. The gate length L2 is the gate length of the reference transistor QREF and it is, for example, 5 .mu.m. .DELTA.L indicates the permissive width against deviation generated in the wafer manufacturing process and it is, for example, 0.05 .mu.m. In a case where the threshold voltage VT10 corresponding to the gate length L1 is, for example, 0.6 V when the gate length is L1, the threshold voltage values VT1L, VT1H, VT2L, VT20 and VT2H corresponding to the gate lengths L1-.DELTA.L, L1+.DELTA.L, L2-.DELTA.L, L2 and L2 +.DELTA.L are 0.45 V, 0.7 V, 0.895 V, 0.90 V and 0.905 V, respectively. In this case, if the power supply voltage is 3.3 V, a distribution width of mutual conductance indicative of the transistor performance is in a range from +24% to -16% with respect to the design mutual conductance of the transistor with the gate length of L1. On the other hand, the distribution width of mutual conductance is in a range of .+-.1.5% with respect to the design mutual conductance of the transistor with the gate length of L2.
In the MOS transistor, because the leak current increases and the element lifetime becomes short if the gate length becomes short. Therefore, the lower limit of the gate length needs to be set from the viewpoint of prevention of malfunction and performance guarantee. In this example, the lower limit value is preferably 0.45 .mu.m, and more preferably 0.47 .mu.m. On the other hand, when the gate length becomes long, there is a problem that the operation speed of the circuit is decreased. Therefore, the upper limit value is preferably 0.55 .mu.m, and more preferably 0.53 .mu.m. Thus, the manufacturing process of the semiconductor integrated circuit device needs to be managed based on these upper and lower limit values. In this conventional example, the threshold voltage of the MOS transistor changes as change of the gate length. The deviation of the gate length is detected using the fact that the change amount of the threshold voltage depends on the gate length, as shown in FIG. 4 and then whether the transistor characteristic is good or wrong is determined.
In the diagnostic circuit which is shown in FIG. 3, it is assumed that the lower limit value of the gate length of the transistor which has been designed with L1=0.5 .mu.m is 0.45 .mu.m. Also, the diagnostic transistor QDDT is designed to have the gate length of L1=0.50 .mu.m and the gate width W1=5.0 .mu.m, and the reference transistor QREF is designed to have the gate length of L2=5.0 .mu.m and the gate width W2=77 .mu.m. In this case, if there is no deviation in the transistor size in the manufacture process, the mutual conductance of the diagnostic transistor QDDT is smaller than the mutual conductance of the reference transistor QREF. As a result, the drain current IREF flowing through the reference transistor QREF is about 1.24 times of the drain current IDDT flowing through the diagnostic transistor QDDT. A Logic output signal of "1" is outputted to the output terminal 5. In the circuit shown in FIG. 2, when the signal which has been outputted to the output terminal 5 of the diagnostic circuit 20 has a logic value of "1" which indicates that the characteristic of the diagnostic transistor QDDT satisfies the manufacture standards, the transistors Q9 and Q10 which compose a tri-state buffer of an output stage are set to the ON state. That is, this tri-state buffer of the output stage is activated such that the output signal determined in accordance with the input signal inputted to the input terminal 1 appears at the external output terminal 2.
On the other hand, when the parameters are changed during the wafer process so that the gate length of the diagnostic transistor QDDT becomes 0.45 .mu.m and the gate length of the reference transistor QREF becomes 4.95 .mu.m, the mutual conductances of the two transistors QDDT and QREF become same. If the gate lengths become further short, the magnitude relation in mutual conductance between the two transistors QDDT and QREF is made inverted. As a result, the mutual conductance of the diagnostic transistor QDDT becomes larger than the mutual conductance of the reference transistor QREF. In this case, the logic output signal on the output terminal 5 of the diagnostic circuit 20 is changed from "1" to "0" so that both of the transistors Q9 and Q10 which compose the tri-state buffer of the output stage are set to the OFF state. For this reason, the external output terminal 2 is set to the high impedance state. Therefore, an output from the external output terminal 2 is inhibited.
As would be understood from the above description of the operation, in the semiconductor integrated circuit device shown in FIG. 2, because the diagnostic circuit 20 self-diagnoses the characteristic of the MOS transistor used in the signal processing circuit 10, it is not necessary to externally input any dedicated signal to operate the diagnostic circuit 20, e.g., the signal TEST in the conventional integrated circuit device shown in FIG. 1. Also, a diagnosis result is represented as a binary signal of "1" or "0". This signal determines the output enable or disable state of the external output terminal 2 of the signal processing circuit 10.
However, the above-mentioned conventional semiconductor integrated circuit device has the following problem. That is, in the conventional semiconductor integrated circuit device shown in FIG. 2, the reference MOS-type field effect transistor QREF is designed such that it is larger several times in the gate length and gate width than the diagnostic transistor QDDT. However, as shown in FIG. 4, since the threshold voltage of the transistor has dependency on the gate length, even if a ratio of the gate length to the gate width in the reference transistor QREF is merely set to the same as that of the diagnostic transistor, the reference transistor QREF cannot be obtained to have the same mutual conductance as the diagnostic transistor QDDT. Therefore, there is a problem that the circuit design to get a desired characteristic is not easy.